How does a 7 nm process work?

The average person might think that making semiconductor chips is like making a cake, right? anti vibration table Layer by layer, it will succeed. But we can still eat our cake if it goes bad? It is impossible to continue developing the semiconductor due to the defective transistors, large leakages, excessive power consumption, and slow development.

Forty years ago, when I started working in the semiconductor industry at United Electronics, semiconductor test the most advanced technology available was 6 microns (or 6,000 nanometers). From there, I progressed to working with 3 microns (or 3,000 nanometers) where engineers utilized light microscopes to detect any issues in the product. This was possible because light has a wavelength of 400 to 800 nanometers. Now, four decades later, the roadmap for semiconductor processes has been outlined from 1,000 nanometers down to as small as 2 nanometers.

If the thinnest point of the process is just 7 nanometers thick, then an insulator is composed of 70 silicon atoms of silicon oxide. Silicon atoms have a diameter of about 0.1 nanometers. As a result, such thin walls are more transparent than 1mm glass, and quantum mechanics tell us that 90% of electrons trapped inside a wall remain inside and 10% are outside. According to quantum mechanics, this phenomenon is inevitable.

In the realm of 7 nm integrated circuit design, voltage probe engineers are faced with the challenge of managing leakage between the D-S components. It's like having to design a bathroom with a constantly dripping faucet. To tackle this issue, logic gates can be used instead, where the rules are not as absolute - 1 no longer equals 100% power and 0 no longer equals 0% power, but rather analog signals of 1 equaling around 70% power and 0 representing approximately 30% leakage. This may seem daunting for those who have only worked with digital circuits, but for those familiar with analog circuits and the significant leakage in ancient germanium transistors (Icbo), it's not as overwhelming. However, for younger individuals growing up in the digital era, this concept may seem maddeningly complex.

In ancient germanium transistors, ICBO is a common heat leak, unrelated to this topic, and won't be discussed in detail here.

Process with a 7nm diameter that is fake

Luckily, TSMC is now recognized for its 7 nm process. However, this designation can be deceiving. While the smallest D-S channel measures 7 nm wide, the actual gate width is only 20 nm and the transistor line width is 40 nm. Additionally, the MOS transistor still measures at 40x60x100 nm in size. This falls short of the true capabilities of producing a quantum communication tunnel effect with minimal leakage. In fact, leakage caused by quantum mechanics amounts to a mere 1%, leaving 99% as usable electricity. Therefore, logic engineers need not worry or panic about this issue.

Nanoprocesses 2/3/5

However, if one day the process truly reaches the so-called 2 nm, and the actual insulation wall is only 6 nm, then the physical phenomena of quantum mechanics will be evident, such as 1 = 60% electricity, 0 = 40% leakage, etc. With 1 = 55% electricity and 0 = 45% leakage, a 3.5nm thick wall would be hilarious and would require next-generation AI.

By then, quantum computers will be in use, and silicon crystal semiconductors will be turned into bone and displayed like vacuum tubes in museums.